1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a redundancy technique for replacing a defective part in a semiconductor memory device.
2. Description of the Related Art
A redundancy circuit for replacing a defective part in a semiconductor memory device is widely known. For example, Japanese Laid Open Patent Application JP-A-Heisei 7-320496 describes a nonvolatile semiconductor memory device provided with such a redundancy circuit. FIG. 1 shows a semiconductor memory device including a feature of the circuit configuration disclosed in the patent document, Japanese Laid Open Patent Application (JP-A-Heisei, 7-320496). The semiconductor memory device is provided with an address comparator 110, an X-predecoder 120, a normal X-main driver 130, a redundancy X-main driver 140, an inverter 150, a memory cell array 160 and a sense amplifier 170.
A case will be described as an example, in which 1024 word lines are provided and the replacement with redundancy word lines is performed with respect to eight word lines. That is, the 1024 word lines WL[1023:0] are provided in a normal region of the memory cell array 160, and eight redundancy word lines RWL[7:0] are provided in a redundancy region of the memory cell array 160. The 1024 word lines are sectioned into 128 sectors each of which includes eight word lines. Among the 128 sectors, a sector including a defective word line or a defective memory cell is hereinafter referred to as a “replacement-target sector”. A rescue of the defective part is carried out by replacing eight word lines WL included in the replacement-target sector with the eight redundancy word lines RWL included in the redundancy region.
An address signal ADD[15:0] is a signal specifying an address of a memory cell to be accessed. In the address signal ADD[15:0], ADD[8:3] of 6 bits is used for selecting any of 64 bit lines. The remaining ADD[15:9, 2:0] of 10 bits is used for selecting any of 1024 word lines WL[1023:0]. More specifically, any one of the 128 sectors is specified by ADD[15:9] of 7 bits, and any one of eight word lines included in the specified sector is specified by ADD[2:0] of 3 bits.
Further, the replacement-target sector in the 128 sectors is specified by a redundancy address signal RedunADD[6:0] of 7 bits. A redundancy flag RedunFLAGZ is a flag indicating whether or not the replacement (rescue) of word lines should be carried out. For example, the replacement is not carried out when the redundancy flag RedunFLAGZ is set to “H (High Level)”, while the replacement is carried out when the redundancy flag RedunFLAGZ is set to “L (Low Level)”.
The address comparator 110 shown in FIG. 1 has a circuit configuration as shown in FIG. 2. The address comparator 110 compares between the address signal ADD[15:9] specifying a sector and the redundancy address signal RedunADD[6:0] specifying the replacement-target sector. More specifically, respective bits of the address signal ADD[15:9] and respective bits of the redundancy address signal RedunADD[6:0] are input to respective of a plurality of EXNOR circuits 111. Respective outputs of the EXNOR circuits 111 and an inversion signal of the redundancy flag RedunFLAGZ are input to a NAND circuit 112. An output of the NAND circuit 112 is input to an inverter 113 and the inverter 113 outputs a hit signal HIT.
When the redundancy flag RedunFLAGZ is “L” and the address signal ADD[15:9] matches the redundancy address signal RedunAdd[6:0] in all bits, the output hit signal HIT is “H”. On the other hand, when the redundancy flag RedunFLAGZ is “H”, or the address signal ADD[15:9] does not match the redundancy address signal RedunAdd[6:0] in at least any one bit, the output hit signal HIT is “L”.
The hit signal HIT is supplied to the redundancy X-main driver 140 and the inverter 150 shown in FIG. 1. The inverter 150 outputs an inversion signal of the hit signal HIT as an inversion hit signal HITB to the X-predecoder 120.
The X-predecoder 120 shown in FIG. 1 has a circuit configuration as shown in FIG. 3. The X-predecoder 120 decodes the address signal ADD[15:9, 2:0]. More specifically, respective bits of the address signal ADD[15:9, 2:0] are input to respective of a plurality of inverters 121, and signals A0B to A15B are output from respective of the plurality of inverters 121. Further, the signals A0B to A15B are input to respective of a plurality of other inverters 121, and signals A0 to A15 are output from respective of the plurality of other inverters 121.
Input to each of eight AND circuits 122 are any of the signals A2B and A2, any of the signals A1B and A1, and any of the signals A0B and A0. Thus, respective of the eight AND circuits 122 generate respective bits of a predecode signal XPA[7:0]. Further, input to each of 16 AND circuits 123 are any of the signals A12B and A12, any of the signals A11B and A11, any of the signals A10B and A10, any of the signals A9B and A9, and the inversion hit signal HITB. Thus, respective of the 16 AND circuits 123 generate respective bits of a predecode signal XPB[15:0]. Further, input to each of eight AND circuits 124 are any of the signals A15B and A15, any of the signals A14B and A14, any of the signals A13B and A13, and the inversion hit signal HITB. Thus, respective of the eight AND circuits 124 generate respective bits of a predecode signal XPC[7:0].
In a case when the inversion hit signal HITB is “H”, any one bit of the predecode signal XPA[7:0], any one bit of the predecode signal XPB[15:0], and any one bit of the predecode signal XPC[7:0] become “H”. Here, the predecode signal XPB[15:0] and the predecode signal XPC[7:0] corresponding to the address signal ADD[15:9] are used for selecting any of the 128 sectors. More specifically, any one of eight blocks each including 128 word lines is selected by the predecode signal XPC[7:0]. Then, any one of 16 sectors included in the selected block is selected by the predecode signal XPB[15:0]. Further, any one of eight word lines included in the selected sector is selected by the predecode signal XPA[7:0] corresponding to the address signal [2:0].
On the other hand, in a case when the inversion hit signal HITB is “L”, all bits of the predecode signal XPB[15:0] and the predecode signal XPC[7:0] become “L”, and thus no sector in the normal region is selected. In other words, when the address signal ADD[15:9] matches the redundancy address signal RedunAdd[6:0] in all bits, no sector in the normal region is selected. As described above, the operation of the X-predecoder 120 depends on the inversion hit signal HITB, and the X-predecoder 120 deactivates the predecode signals XPB and XPC when the replacement-target sector is specified by the address signal ADD.
The normal X-main driver 130 and the redundancy X-main driver 140 shown in FIG. 1 have a circuit configuration as shown in FIG. 4. The normal X-main driver 130 is provided with 1024 word line drivers 131 connected to respective of the word lines WL[1023:0] of the normal region and 1024 AND circuits 132 connected to respective of the word line drivers 131. Input to each of the 1024 AND circuits 132 are any bit of the predecode signal XPA[7:0], any bit of the predecode signal XPB[15:0], and any bit of the predecode signal XPC[7:0]. An output of each AND circuit 132 is input to the corresponding word line driver 131.
The redundancy X-main driver 140 is provided with eight word line drivers 131 connected to respective of the redundancy word lines RWL[7:0] of the redundancy region and eight AND circuits 142 connected to respective of the word line drivers 131. Input to each of the eight AND circuits 142 are the hit signal HIT as well as any bit of the predecode signal XPA[7:0]. An output of each AND circuit 142 is input to the corresponding word line driver 131.
In a case when the HIT signal is “L”, the redundancy X-main driver 140 is deactivated. In this case, one word line driver 131 corresponding to a memory cell specified by the address signal ADD[15:9, 2:0] is selected in the normal X-main driver 130. On the other hand, in a case when the HIT signal is “H”, namely, in a case when the replacement-target sector is specified, all the predecode signals XPB and XPC become “L” and hence no word line driver 131 is selected in the normal X-main driver 130. Instead, the redundancy X-main driver 140 is activated, and one word line driver 131 specified by the predecode signal XPA[7:0] is selected in the redundancy X-main driver 140. The selected one word line driver 131 drives the corresponding one word line WL or one redundancy word line RWL. In this manner, the replacement of the word line WL in the replacement-target sector with the redundancy word line RWL is realized.
Next, an operation from an address determination to the word line driving will be explained below with reference to a timing chart shown in FIG. 5. In the example shown below, the following situation is considered: when the address signal ADD[15:0] is “0000H” or “FFFFH”, a memory cell included in a sector other than the replacement-target sector is designated. When the address signal ADD[15:0] is “0200H”, a memory cell included in the replacement-target sector is designated. When the address signal ADD[15:0] is “0000H”, a word line WL0 is driven. When the address signal ADD[15:0] is “0200H”, a redundancy word line RWL0 is driven. When the address signal ADD[15:0] is “FFFFH”, a word line WL1023 is driven. In the X-predecoder 120, the time from the input of the address signal ADD[15:0] and the inversion hit signal HITB to the output of the predecode signals XPA to XPC is 4 ns, which is referred to as a “predecode time”. Furthermore, in the address comparator 110, the time from the input of the address signal ADD[15:9] to the output of the hit signal HIT is 4 ns, which is referred to as a “address comparison time”.
With reference to FIG. 5, the redundancy flag RedunFLAGZ changes to “L” at time t0, which enables the replacement of word lines. Further, the redundancy address signal RedunADD[6:0] of “0000001”, which is the same as the upper 7 bits of “0200H”, is input to the address comparator 110.
Next, at time t1, a read address is determined and the address signal ADD[15:0] becomes “0000H”. In this case, since the address signal ADD[15:9] does not match the redundancy address signal RedunADD[6:0], the hit signal HIT remains “L”. At time t2 the predecode time (4 ns) after the time t1, the X-predecoder 120 outputs the predecode signals XPA, XPB and XPC to the normal X-main driver 130 (only the XPC0 and XPC7 are shown in FIG. 5). As a result, the word line WL0 in the normal region is driven.
At time t3, a next read address is determined and the address signal ADD[15:0] becomes “0200H”. In this case, the address signal ADD[15:9] matches the redundancy address signal RedunADD[6:0]. Therefore, at time t4 the address comparison time (4 ns) after the time t3, the hit signal HIT becomes “H”. As a result, the redundancy X-main driver 140 is activated, and the redundancy word line RWL0 in the redundancy region is driven. Further, the inversion hit signal HITB becomes “L” at the time t4, and the predecode signal XPC0 becomes “L”. As a result, the driving of the word line WL0 in the normal region is stopped.
At time t5, a next read address is determined and the address signal ADD[15:0] becomes “FFFFH”. In this case, the address signal ADD[15:9] does not match the redundancy address signal RedunADD[6:0]. Therefore, at time t6 the address comparison time (4 ns) after the time t5, the hit signal HIT becomes “L”. As a result, the redundancy X-main driver 140 is deactivated, and the driving of the redundancy word line RWL0 in the redundancy region is stopped. Further, the inversion hit signal HITB becomes “H” at the time t6, and the X-predecoder 120 starts the predecoding operation. At time t7 the predecode time (4 ns) after the time t6, the predecode signal XPC7 becomes “H”. As a result, the word line WL1023 in the normal region is driven.
It should be noted that the bit line is selected in accordance with the address signal ADD[8:3] by a Y-decoder and a Y-selector which are not shown in FIG. 1. As a result, a target memory cell specified by the address signal ADD[15:0] is selected. A read data BIT read out from the selected memory cell is output as an output data DOUT through the sense amplifier 170.